• Some  functionality enhancement of the existing device. This functionality enhancement change may be too small to undergo all the process steps again

  
  

• There may be some design bug that needs to be fixed and was caught very late in     the design cycle. It is very costly to re-run all the process cycle steps for each bug in terms of time and cost. Hence, these changes need to be taken incrementally.

  
  

• All layers ECO: In this, the design change is implemented using all layers. This kind of ECO provides advantage in terms     of cycle time and engineering costs. It is implemented whenever the change     is not possible to be carried out without all layer change e.g. there is     an updation in a hard macro cell or the change may require updation of 100’s of cells. It is almost impossible to contain such a large change to a few layers only.

  
  

• Metal-only ECO: As discussed above, due to incurring  costs, sometimes, it may not be practical to use all the layers (base  metal) to do the ECO. In that case, to minimize the cost, it is required     to be completed with changes only in minimal number of metal layers. These     days, it is expected that every design will be re-opened for the ECOs. So, an adequate number of spare cells are sprinkled during the implementation  all over the design to be used later on. These cells are spread uniformly over the design. The inputs of these cells are tied. Whenever the need for an ECO arises, the cells to be implemented can be mapped into the existing spare cells. Hence, there is no need to change the base layers in such a case. Only the connections need to be updated which can be done by changing the metal layers only. Hence, the base layer cost is saved.

  
  

1. The RTL with ECO implemented is synthesized and compared with the golden netlist.

   
   

2. The delta is implemented into the golden netlist. The modified netlist is then again      compared with the synthesized netlist to ensure the logic has been      implemented correctly.

   
   

3. The logic is the placed incrementally. However, if it is metal-only ECO, spare cells in      the proximity of the changed logic are found out.

   
   

4. The connections are, then, modified in metal layers.

   
   

Metal ECO - the process

Spare Cells

• Those used deliberately as spare cells in the design: As discussed earlier, most of the designs today have spare cells sprinkled uniformly. These cells have inputs and outputs tied to either ‘0’ or ‘1’ so that they contribute minimum to static and dynamic power.

  
  

• Those converted into spare cells due to design changes: There may be a case that a cell that is being identified as a spare now was a main cell in the past. Due to some design changes, the cell might have been replaced by another cell. Also, some cells have floating outputs. These can be used as spare cells. We can also use the used buffers as spare cells if removing the buffer does not introduce any setup/hold violation in the design.

  
  

• Reusability: A design change can be carried out using metal layers only. So, the base layers can be re-used for fabrication of new chips.

  
  

• Cost reduction: Significant amount of money is saved both in terms of engineering and manufacture costs.

  
  

• Design flexibility: As there are spare cells, small changes can be taken into the design without much difficulty. Hence, the presence of spare cells provides flexibility to the design.

  
  

• Cycle time reduction: Nowadays, there is a trend to tape out base layers to the foundry for fabrication as masks are not prepared in parallel. In the meantime, the timing violations/design changes are being carried out in metal layers. Hence, there is cycle time reduction of one to two weeks.

  
  

• Contribution to static power: Each spare cell has its static power dissipation. Hence, greater amount of spare cells contribute more to power. But, in general, this amount of power is insignificant in comparison to total power. Spare cells should be added keeping into consideration their contribution to power.

  
  

• Area: Spare cells occupy area on the chip. So, more spare cells mean more density of cells.