我用的2440開(kāi)發(fā)板，取名為TX2440。

第一步：U-Boot -1.1.6需要交叉編譯工3.3.2，首先安裝arm-linux-gcc-3.3.2.tar.bz2。

第二步：將U-Boot-1.1.6放入smb服務(wù)器，在linux下解壓。
（1）到U-boot-1.1.6目錄下：cd u-boot-1.1.6
修改cpu/arm920t下的config.mk文件，將其中的-msoft-float注釋掉：
vi cpu/arm920t/config.mk
#-msoft-float（意思是不使用軟浮點(diǎn)進(jìn)行編譯。我們使用 的還是硬浮點(diǎn)）
（2）修改U-boot-1.1.6目錄下Makefile:
在smdk2410_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
加上
TX2440_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t TX2440 NULL s3c24x0
各項(xiàng)的意思如下：
arm：CPU 的架構(gòu)（ARCH）
arm920t：CPU的類型（CPU），其對(duì)應(yīng)于cpu/arm920t子目錄
TX2440：開(kāi)發(fā)板的型號(hào)（BOARD），對(duì)應(yīng)于board/TX2440目錄
NULL：開(kāi)發(fā)者/或經(jīng)銷商（vender）
s3c24x0：片上系統(tǒng)（SOC）

在第128行：
Ifeq（$(ARCH),arm）
CROSS_COMPILE=arm-linux-
指定交叉編譯器，我們使用的是3.3.2，這里也可以寫絕對(duì)路徑
（3）在board目錄下，①新建自己的開(kāi)發(fā)板目錄TX2440，把smdk2410目錄下所有的文件拷到TX2440; mv smdk2410 TX2440
②把smdk2410.c改為TX2440.c ：mv smdk2410.c TX2440.c
③修改目錄下的Makefile，把smdk2410.o改成TX2440.o
COBJS :=TX2440.o flash.o
④將board目錄下所有文件夾都刪除，只留TX2440:
mv TX2440 ..
rm –rf *
mv ../TX2440 ./
(4) 在include/configs目錄下創(chuàng)建板子的配置頭文件，把smdk2410.h改名為TX2440.h，再把所有的文件全部刪除，只留TX2440.h
mvsmdk2410.hTX2440.h
mvTX2440.h..
rm-rf*
mv../TX2440.h./

測(cè)試能否編譯成功：
執(zhí)行make TX2440_config
出現(xiàn)make: execvp: …………/mkconfig: 權(quán)限不夠
查看mkconfig的權(quán)限，發(fā)現(xiàn)沒(méi)有可執(zhí)行權(quán)限，用chmod 764 mkconfig加上權(quán)限
然后再make，成功后可出現(xiàn) Configuring for TX2440 board.....

第三步：修改SDRAM配置
①再board/TX2440/lowlevel_init.S中，檢查#defineB6_BWSON (DW32)
位寬為32位（因?yàn)镾DRAM是2片16位的k4s561632即1片32位的）
②根據(jù)HCLK設(shè)置SDRAM的刷新參數(shù)，主要是REFCNT寄存器，開(kāi)發(fā)板HCLK為100M
將#define REFCNT1113改為#defineREFCNT0x4f4

第四步：增加對(duì)s3c2440的支持，2440的時(shí)鐘計(jì)算公式、NAND操作和2410不太一樣。對(duì)于2440開(kāi)發(fā)板，將FCLK設(shè)為400MHz,分頻比為FCLK：HCLK：PCLK=1:4:8

<1>時(shí)鐘計(jì)算
①修改board/TX2440/TX2440.c中的board_init函數(shù)

/* S3C2440: Mpll,Upll = (2*m * Fin) / (p * 2^s)

* m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2

*/

#define S3C2440_MPLL_400MHZ ((0x7f<<12)|(0x02<<4)|(0x01))

#define S3C2440_UPLL_48MHZ ((0x38<<12)|(0x02<<4)|(0x02))

#define S3C2440_CLKDIV 0x05 /* FCLK:HCLK:PCLK = 1:4:8 */

/* S3C2410: Mpll,Upll = (m * Fin) / (p * 2^s)

* m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2

*/

#define S3C2410_MPLL_200MHZ ((0x5c<<12)|(0x04<<4)|(0x00))

#define S3C2410_UPLL_48MHZ ((0x28<<12)|(0x01<<4)|(0x02))

#define S3C2410_CLKDIV 0x03 /* FCLK:HCLK:PCLK = 1:2:4 */

int board_init (void)

{

S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();

S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

/* set up the I/O ports */

gpio->GPACON = 0x007FFFFF;

gpio->GPBCON = 0x00044555;

gpio->GPBUP = 0x000007FF;

gpio->GPCCON = 0xAAAAAAAA;

gpio->GPCUP = 0x0000FFFF;

gpio->GPDCON = 0xAAAAAAAA;

gpio->GPDUP = 0x0000FFFF;

gpio->GPECON = 0xAAAAAAAA;

gpio->GPEUP = 0x0000FFFF;

gpio->GPFCON = 0x000055AA;

gpio->GPFUP = 0x000000FF;

gpio->GPGCON = 0xFF95FFBA;

gpio->GPGUP = 0x0000FFFF;

gpio->GPHCON = 0x002AFAAA;

gpio->GPHUP = 0x000007FF;

/*support both of S3C2410 and S3C2440*/

if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002))

{

/*FCLK:HCLK:PCLK = 1:2:4*/

clk_power->CLKDIVN = S3C2410_CLKDIV;

/* change to asynchronous bus mod */

__asm__( "mrc p15, 0, r1, c1, c0, 0n" /* read ctrl register */

"orr r1, r1, #0xc0000000n" /* Asynchronous */

"mcr p15, 0, r1, c1, c0, 0n" /* write ctrl register */

:::"r1"

);

/* to reduce PLL lock time, adjust the LOCKTIME register */

clk_power->LOCKTIME = 0xFFFFFF;

/* configure MPLL */

clk_power->MPLLCON = S3C2410_MPLL_200MHZ;

/* some delay between MPLL and UPLL */

delay (4000);

/* configure UPLL */

clk_power->UPLLCON = S3C2410_UPLL_48MHZ;

/* some delay between MPLL and UPLL */

delay (8000);

/* arch number of SMDK2410-Board */

gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;

}

else

{

/* FCLK:HCLK:PCLK = 1:4:8 */

clk_power->CLKDIVN = S3C2440_CLKDIV;

/* change to asynchronous bus mod */

__asm__( "mrc p15, 0, r1, c1, c0, 0n" /* read ctrl register */

"orr r1, r1, #0xc0000000n" /* Asynchronous */

"mcr p15, 0, r1, c1, c0, 0n" /* write ctrl register */

:::"r1"

);

/* to reduce PLL lock time, adjust the LOCKTIME register */

clk_power->LOCKTIME = 0xFFFFFF;

/* configure MPLL */

clk_power->MPLLCON = S3C2440_MPLL_400MHZ;

/* some delay between MPLL and UPLL */

delay (4000);

/* configure UPLL */

clk_power->UPLLCON = S3C2440_UPLL_48MHZ;

/* some delay between MPLL and UPLL */

delay (8000);

/* arch number of SMDK2440-Board */

gd->bd->bi_arch_number = MACH_TYPE_S3C2440;

}

/* adress of boot parameters */

gd->bd->bi_boot_params = 0x30000100;

icache_enable();

dcache_enable();

return 0;

}

②在cpu/arm920t/s3c24X0/speed.c中修改：

在程序開(kāi)頭增加一行DECLARE_GLOBAL_DATA_PTR;，這樣才可以使用gd變量

修改get_PLLCLK函數(shù)：

static ulong get_PLLCLK(int pllreg)

{

S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();

ulong r, m, p, s;

if (pllreg == MPLL)

r = clk_power->MPLLCON;

else i